In an effort to increase I/O bandwidth in high performance processor based systems, a number of companies have developed the HyperTransport (“HT”) I/O interconnect structure. Briefly, the HT I/O interconnect structure is a scalable device level architecture that provides a significant increase in transaction throughput over existing I/O bus architectures such as Peripheral Component interconnect (“PCT”) and Advanced Graphics Port (“AGP”).
The foundation of the HT I/O interconnect is dual point-to-point unidirectional links consisting of a data path, control signals, and clock signals. The HT I/O interconnect can provide both point-to-point links and a scalable network topology using HT I/O switching fabrics. Thus, an HT based system can be expanded using HT switches to support multilevel, highly complex systems.
Communications between multiple HT I/O devices are known as data streams. Each data stream contains one or more packets of information. Each packet of information contains a packet ID and a data payload. The packet ID is also commonly referred to as a unit ID. Because all packets are transferred to or from a host bridge, the packet ID provides information that can be utilized to determine the source or destination of the packet. A more detailed description of the HT I/O interconnect structure is presented in Appendix A.
While HT switches that handle multiple HT I/O data streams and manage the interconnection between attached HT I/O devices have been proposed in concept, no methods for managing configuration of such switches are known. Similarly, no methods for efficiently forwarding packets through such switches are known. Thus, a need exists for efficiently managing configuration of and packet forwarding through HT switches.